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2-/3-/4-phase synchronous buck controller for imvp-5 cpus ADP3206 rev . 0 information furnished by analog devices is believed to be a ccurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to chan ge without notice. no license is granted by implication or otherwise under any patent or patent ri ghts of analog devices. trademarks and registered trademarks are the prop erty of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.326.8703 ? 2004 analog devices, inc. all rights reserved. features selectable 2-, 3-, or 4-phase operation at up to 1 mhz per phase 6-bit digitally programmable 0.8375 v to 1.6 v output 10 mv dac accuracy over temperature logic-level pwm outputs for interface to external high power drivers active current/thermal balancing between phases built-in power good/crow bar blanking supports on-the-fly vid code changes programmable deep sleep offset and deeper sleep reference voltage programmable soft transient control to minimize inrush currents during output voltage changes programmable short circuit protection with programmable latch-off delay applications desk-note and notebook pc power supplies for imvp-5 compliant intel? processors general description the ADP3206 is a highly efficient multiphase synchronous buck-switching regulator controller optimized for converting the notebook main supply into the core supply voltage required by imvp-5 intel processors. it uses an internal 6-bit dac to read a voltage identification (vid) code directly from the processor, which is used to set the output voltage between 0.8375 v and 1.6 v, and uses a multimode pwm architecture to drive the logic-level outputs at a programmable switching frequency that can be optimized for vr size and efficiency. the phase relationship of the output signals can be programmed to provide 2-, 3-, or 4-phase operation. the ADP3206 includes programmable no-load offset and slope functions to adjust the output voltage as a function of the load current so that it is always optimally positioned for a system transient. the ADP3206 also provides accurate and reliable short circuit protection, adjustable current limiting, deep sleep and deeper sleep programming inputs, and a delayed power good output that accommodates on-the-fly output voltage changes requested by the cpu. ADP3206 is specified over the commercial temperature range of 0c to 100c and is available in a 40-lead lfcsp package. functional block diagram dpslp sd 12 24 22 21 13 35 16 15 23 14 17 4 2 7 40 39 38 37 36 1 6 30 29 5 8 9 10 11 3 20 18 19 25 26 27 28 31 32 33 34 od2 od1 soft start delay thermal throttling control oscillator gnd vcc rampadj rt ADP3206 delay pwrgd ilimit ttmask ttsense vrtt pwm2 fb dprslp dpset dprset pgmask stset 04651-0-001 pwm3 pwm4 sw1 cssum cscomp sw2 sw3 sw4 csref pwm1 vid0 vid1 vid2 vid3 vid5 vid4 fbrtn ref comp csref current- limiting circuit crowbar current limit current- balancing circuit 2-/3-/4-phase driver logic en set reset reset reset reset deep/ deeper sleep control precision reference uvlo shutdown and bias cmp cmp cmp cmp vid dac figure 1.
ADP3206 rev. 0| page 2 of 32 table of contents specifications..................................................................................... 3 test circuits....................................................................................... 6 absolute maximum ratings............................................................ 7 pin configuration and function descriptions............................. 8 typical performance characteristics ........................................... 10 theory of operation ...................................................................... 11 number of phases ...................................................................... 11 master clock frequency............................................................ 11 output voltage differential sensing ........................................ 11 output current sensing ............................................................ 11 active impedance control mode............................................. 12 current control mode and thermal balance ........................ 12 voltage control mode................................................................ 12 deep sleep and deeper sleep settings..................................... 13 soft-start...................................................................................... 14 current limit, short circuit, and latch-off protection ....... 14 dynamic vid.............................................................................. 15 power good monitoring ........................................................... 15 output crowbar ......................................................................... 15 output enable and uvlo ........................................................ 15 thermal throttling control...................................................... 15 application information................................................................ 18 setting the clock frequency ..................................................... 18 soft-start, power good, and current limit latch-off delay times................................................................................. 18 inductor selection ...................................................................... 18 selecting a standard inductor................................................... 19 output droop resistance.......................................................... 19 inductor dcr temperature correction ................................. 20 output offset .............................................................................. 20 c out selection ............................................................................. 21 power mosfets........................................................................ 21 ramp resistor selection............................................................ 22 comp pin ramp ....................................................................... 22 current limit setpoint .............................................................. 22 feedback loop compensation design.................................... 23 c in selection and input current di/dt reduction.................. 23 deepersleep voltage and transient setting............................. 24 deepsleep offset voltage setting ............................................. 25 pwrgd mask timer setting ................................................... 25 selecting thermal monitor components ............................... 25 tuning procedure for ADP3206............................................... 26 layout and component placement ............................................. 28 general recommendations....................................................... 28 power circuitry .......................................................................... 28 signal circuitry........................................................................... 28 outline dimensions ....................................................................... 29 ordering guide .......................................................................... 30 revision history 4/04revision 0: initial version
ADP3206 rev. 0| page 3 of 32 specifications table 1. vcc = 5 v, fbrtn = dprslp = gnd, sd = 1.2 v, dpslp = 3.3 v, t a = 0 o c to 100 o c, unless otherwise noted. 1 parameter symbol conditions min typ max unit reference and vid dac reference output voltage v ref i ref = 100 a 2.95 3.0 3.05 v i ref = 4 ma 2.93 3.0 3.07 v output current range i ref 0 4 ma normal mode output accuracy v fb relative to nominal dac output, referenced to fbrtn, dprslp = 0 v ? 10 +10 mv deeper sleep output accuracy v stset relative to dprset input, referenced to fbrtn, dprslp = 3.3 v ? 5 +5 mv input low voltage v il(vid) 0.4 v input high voltage v ih(vid) 0.8 v input current, input voltage low i il(vid) vid(x) = 0 v ? 20 ? 30 a input current, input voltage high i ih(vid) vid(x) = 1.25 v 5 15 a pull-up resistance r vid 35 60 k ? internal pull-up voltage 0.9 1.1 1.25 v vid transition delay time 1 vid change to dacref change 400 ns no cpu detection turn-off delay time 2 vid change to 1111 to pwm going low 400 ns deepsleep/deepersleep control dpslp, dprslp input low voltage v il 0.8 v input high voltage v ih 2.0 v input current ? 1 1 a od1, od2 output voltage low v ol i odx (sink) = 400 a 80 500 mv output voltage high v oh i odx (source) = 400 a 4.0 5.0 v dpset output voltage v dpset dpset C nominal vid output ? 70 +70 mv output current range i dpset 0 100 a dprset input voltage range v dprset 0.5 1.0 v input current i dprset ? 1 1 a stset minimum capacitance c stet 100 pf transient time dpset = 0.75 v 100 s nominal vid output = 1.55 v, c stset = 1.5 nf output voltage range 0.5 3 v output current i stset dpset = 0.75 v, dprslp C 3.3 v v stset = 2 v ? 19 ? 16 ? 13 a v stset = 0.5 v 13 16 19 a thermal throttling control ttsense voltage range 0 2 v ttsense threshold voltage 1.46 1.5 1.54 v ttsense bias current ? 1 1 a ttmask threshold voltage 1.45 1.5 1.55 v ttmask output low voltage ttsense static, i ttmask(sink) = 1 ma 200 mv vrtt output voltage low v ol i vrtt(sink) = 200 a 100 500 mv vrtt output voltage high v oh i vrtt(source) = 200 a 4.0 5.0 v
ADP3206 rev. 0| page 4 of 32 parameter symbol conditions min typ max unit error amplifier output voltage range v comp 0.8 3.3 v line regulation ? v fb vcc = 4.5 v to 5.5 v 0.05 % fb input bias current i fb dpslp = 3.3 v 14 16 18 a dpslp = drslp = 0 v, i dpset = 60 a 70 75 80 a fbrtn current i fbrtn 85 120 a output current i o(err) fb forced to v out = 3% 500 a gain bandwidth product gbw (err) comp = fb 20 mhz slew rate c comp = 10 pf 50 v/ s oscillator frequency range 2 f osc 0.25 4 mhz frequency variation f phase t a = +25 c, r t = 250 k ? , 4-phase 155 200 245 khz t a = +25 c, r t = 115 k ? , 4-phase 400 khz t a = +25 c, r t = 75 k ? , 4-phase 600 khz output voltage vrt r t = 100 k ? to gnd 1.9 2.0 2.1 v rampadj output voltage v rampadj rampadj = fb ? 50 +50 mv rampadj input current range i rampadj 100 a current sense amplifier offset voltage v os(csa) cssum C csref, see figure 1 ? 1.5 +1.5 mv gain bandwidth product gbw( csa) 10 mhz slew rate c cscomp = 10 pf 25 v/ s input common mode range cssum and csref 0 3 v positioning accuracy ? v fb fb C v vid , see figure 2 ? 75 ? 80 ? 85 mv cssum bias current i cssum 20 100 na csref bias current i csref 0.5 5 a output current 2 i cscomp csamp unity gain sourcing 500 a sinking ? 300 a current balance circuit common mode range v sw(x)cm ? 600 +200 mv input resistant r sw(x) s w(x) = 0 v 22 32 42 k ? input current i sw(x) s w(x) = 0 v 4 7 10 a input current matching ? i sw(x) s w(x) = 0 v ? 5 +5 % current limit comparator output voltage v ilimit r ilimit = 200 k ? 0.95 1 1.05 v output current i ilimit r ilimit = 200 k ? 5 a current limit threshold voltage v cl v csref C v cscomp , r ilimit = 200 k ? 4 phase dprslp = 0 v 105 120 145 mv dprslp = 3.3 v 15 30 45 mv latch-off delay threshold v delay in current limit 1.7 1.8 1.9 v latch-off delay time t delay r delay = 250 k ? c delay = 4.7 nf 1.2 ms soft start output current, soft-start mode i delay(ss) during start-up, delay < 2.8 v 15 20 25 a output voltage v delay 3 v soft-start delay time t delay(ss) r delay = 250 k ? , c delay = 4.7 nf, vid code = 011111 600 s
ADP3206 rev. 0| page 5 of 32 parameter symbol conditions min typ max unit shutdown input input low voltage v il( sd ) 0.4 v input high voltage v ih( sd ) 0.8 v input current, input voltage low i il( sd ) sd = 0 v ? 1 1 a input current, input voltage high i ih( sd ) sd = 1.25 v 10 25 a power good comparator undervoltage threshold v pwrgd(uv) relative to nominal output ? 200 ? 250 ? 300 mv overvoltage threshold v pwrgd(ov) relative to nominal output 100 150 200 mv output low voltage v ol(pwrgd) i pwrgd(sink) = 4 ma 150 400 mv power good delay time vid code changing c pgmask = 150 pf 90 s vid code static 200 ns crowbar trip point v crowbar relative to nominal output 100 150 200 mv crowbar reset point 350 450 550 mv crowbar delay time t crowbar overvoltage to pwm going low vid code changing c pgmask = 150 pf 90 s vid code static 400 ns power good masking threshold voltage 2.85 3 3.15 v output current dprslp or vid changing, 3.5 5 6.5 a v pgmask = 0 v dprslp or vid static, 500 a v pgmask = 0.5 v pwm outputs output voltage low v ol(pwm) i pwm(sink) = 400 a 100 500 mv output voltage high v oh(pwm) i pwm(source) = 400 a 4.0 5.0 v supply supply voltage range v cc 4.5 5.5 v supply current i cc 3.5 6 ma uvlo threshold voltage v uvlo vcc rising 3.6 3.8 4.1 v uvlo hysteresis ? v uvlo 50 100 150 mv 1 all limits at temperature extremes ar e guaranteed via correlation using standard statistical quality control (sqc). 2 guaranteed by design or bench characterization, not production tested.
ADP3206 rev. 0| page 6 of 32 test circuits 250k ? 5v 1.25v 1 f + 100nf 100nf 6-bit code 250k ? 20k ? 1k ? 4.7nf ADP3206 top view pin 1 indicator 1 2 3 4 5 6 7 8 9 10 30 29 28 27 26 25 24 23 22 21 40 39 38 37 36 35 34 33 32 31 11 12 13 14 15 16 17 18 19 20 04651-0-002 figure 2. closed-loop output voltage accuracy + ? cssum 20 cscomp 19 35 vcc csref 18 gnd 21 39k ? 100nf 1k ? 1.0v ADP3206 5v v os = cscomp ? 1v 40 04651-0-003 figure 3. current sense amplifier v os + ? cssum 20 cscomp 19 35 vcc csref 18 comp 3 fb 4 gnd 21 200k ? 10k ? 200k ? 1.0v ADP3206 ? v 5v 100nf ? v fb = fb ? v = 80mv ? fb ? v = 0mv 04651-0-004 figure 4. positioning voltage
ADP3206 rev. 0| page 7 of 32 absolute maximum ratings table 2. parameter rating vcc C0.3 v to + 6 v fbrtn C0.3 v to + 0.3 v sw1 C sw4 C5 v to + 25 v all other inputs & outputs C0.3 v to + 6 v operating ambient temperature range 0c to +100c operating junction temperature 125c storage temperature range C65c to +150c ja 100c/w lead temperature range (soldering 10 sec) 300c infrared (15 sec) 260c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. absolute maximum ratings apply individually only, not in combination. unless otherwise specified all other voltages are referenced to gnd. esd caution esd (electrostatic discharge) sensitive device. electros tatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
ADP3206 rev. 0| page 8 of 32 pin configuration and fu nction descriptions pin indicator top view 04651-0-005 28 sw1 27 sw2 26 sw3 25 sw4 24 vrtt 23 ttsense 22 ttmask 21 gnd fbrtn 2 fb 3 comp 4 pgmask 5 stset 6 ref 7 dprset 8 dpset 10 dprslp 9 vid5 1 37 vid3 pwrgd 12 delay 14 csref 18 cssum 19 cscomp 20 rt 15 dpsslp 11 sd 13 36 vid4 35 vcc 34 pwm1 39 vid1 33 pwm2 32 pwm3 31 pwm4 ADP3206 rampadj 16 ilimit 17 29 od2 30 od1 38 vid2 40 vid0 figure 5. pin configuration table 3. pin function descriptions pin no. neonic description 1, 36 to 40 vid5, vid4 to vid0 voltage identification dac inputs. these six pins are pulle d up to an internal refere nce, providing a logic 1 if left open. when in normal operation mode, the dac o utput programs the fb regulation voltage from 0.8375 v to 1.6 v. leaving all vid4 through vid0 open result s in the ADP3206 going into a no cpu mode, shutting off its pwm outputs. 2 fbrtn feedback return. vid dac and error amplifier reference for remote sensin g of the output voltage. 3 fb feedback input. error amplifier input for remote sensing of the output volt age. an external resistor between this pin and the output voltage sets the no-load offset point. 4 comp error amplifier outp ut and compensation point. 5 pgmask power good masking. a capacitor connected between this pin and gnd sets the power good comparator masking time during dprslp and vid pin transitions. 6 stset soft transient setting input. a capa citor connected between this pin and gnd controls the slew rate of the output voltage during transitions between various operating modes. 7 ref internal 3 v reference output. 8 dprset deeper sleep voltage setting input used as the dac reference voltage when dprslp is asserted. 9 dprslp deeper sleep control input. 10 dpset deep sleep offset voltage setting in put. the offset programmed by a resistor connected between this pin and gnd is activated when dpslp is asserted. 11 dpslp deep sleep control input. 12 pwrgd power good output. open drain output that signals when the output voltage is outside of the proper operating range. 13 sd power supply enable input. pulling this pin to gnd disables the pwm outputs. 14 delay soft-start delay and current limit la tch-off delay setting input. an exte rnal resistor/capacitor connected between this pin and gnd sets the soft-start ramp-up time and the o vercurrent latch-off delay time. 15 rt frequency setting resistor input. an external resistor connected between this pin an d gnd sets the oscillator frequency of the device. 16 rampadj pwm ramp current input. an external resistor from the converter inp ut voltage to this pi n sets the internal pwm ramp. 17 ilimit current limit set point. an external resistor from th is pin to gnd sets the curre nt limit threshold of the converter. 18 csref current sense reference voltage input. the voltage on th is pin is used as the reference for the current sense amplifier and the power good and crowbar functions. th is pin should be connected to the common point of the output inductors. 19 cssum current sense summing node. external resistors from each switch node to this pin sum the average inductor currents together to measur e the total output current.
ADP3206 rev. 0| page 9 of 32 pin no. mnemonic description 20 cscomp current sense compensation point. a resistor and capaci tor from this pin to cssum determines the slope of the load line and the positioning loop response time. 21 gnd ground. all internal biasing and the logic output si gnals of the device are referenced to this ground. 22 ttmask thermal throttling masking time setting input. an external resistor from this pin to vcc and an external capacitor to gnd set the delay time during which the vrtt output is masked. this delay is triggered by the assertion or de-assertion of vrtt. 23 ttsense vr hot thermal throttling sens e input. this pin monitors the common tap point of an external resistor- thermistor voltage divider network and ca uses vrtt output signal to go high if the remotely sensed hot spot temperature exceeds the programmed temperature threshold. 24 vrtt voltage regulator thermal throttling o utput. this logic output alerts the cp u that the temperature at one of the designated monitoring points has exc eeded the programmed temperature threshold. 25-28 sw4 C sw1 current balance inputs. inputs for meas uring the current level in each phas e. the sw pins of unused phases should be left open. 29 od2 this pin is actively pulled low under the same conditions as those of od1 . in addition, this pin is actively pulled low when dprslp is asserted. this pin is normally connected to the sd input of the drivers for phases 2 through 4. 30 od1 this pin is actively pulled low when the ADP3206 sd input is low, or when vcc is below its uvlo threshold to signal to the driver ic that the driver high-side an d low-side outputs should go low. this pin is normally connected to the sd input of the phase 1 driver. 31-34 pwm4 C pwm1 logic-level pwm outputs. each output connects to the input of an ex ternal mosfet driver. connecting the pwm3 and/or pwm4 outputs to gnd ca uses that phase to turn off, allo wing the ADP3206 to operate as a 2-, 3-, or 4-phase controller. 35 vcc supply voltage for the device.
ADP3206 rev. 0| page 10 of 32 typical performance characteristics 4 3 2 1 0 master clock frequency (mhz) r t value (k ? ) 0 50 100 150 200 250 300 04651-0-006 figure 6. master clock frequency vs. r t 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 3.9 3.8 3.7 3.6 3.5 3.4 3.3 3.2 supply current (ma) master clock frequency (mhz) ta = 25c 4-phase operation 04651-0-007 figure 7. supply current vs. oscillator frequency
ADP3206 rev. 0| page 11 of 32 theory of operation the ADP3206 combines a multimode, fixed frequency pwm control with multiphase logic outputs for use in 2-, 3-, and 4-phase synchronous buck cpu core supply power converters. the internal 6-bit vid dac conforms to intel's imvp-5 specifications. multiphase operation is important for producing the high currents and low voltages demanded by today's microprocessors. handling the high currents in a single-phase converter would place high thermal demands on the components in the system such as the inductors and mosfets. the multimode control of the ADP3206 ensures a stable, high performance topology for ? balancing currents and thermals between phases ? high speed response at the lowest possible switching frequency and output decoupling ? minimizing thermal switching losses due to lower frequency operation ? tight load line regulation and accuracy ? high current output from having up to 4 phase operation ? reduced output ripple due to multiphase cancellation ? pc board layout noise immunity ? ease of use and design due to independent component selection ? flexibility in operation for tailoring design to low cost or high performance number of phases the number of operational phases and their phase relationship is determined by internal circuitry that monitors the pwm outputs. normally, the ADP3206 operates as a 4-phase pwm controller. grounding the pwm4 pin programs 3-phase operation, and grounding the pwm3 and pwm4 pins programs 2-phase operation. when the ADP3206 is enabled, the controller outputs a voltage on pwm3 and pwm4 that is approximately 550 mv. an internal comparator checks each pin's voltage versus a threshold of 300 mv. if the pin is grounded, then it is below the threshold and the phase is disabled. the output impedance of the pwm pin is approximately 5 k ? during the phase detect. any external pull-down resistance connected to the pwm pin should not be less than 25 k ? to ensure proper phase detection. the phase detection is made during the first two clock cycles of the internal oscillator. after this time, if the pwm output was not grounded, then it switches between 0 v and 5 v. if the pwm output was grounded, then switching to the pin remains off. the pwm outputs are logic-level devices intended for driving external gate drivers such as the adp3419. because each phase is monitored independently, operation approaching 100% duty cycle is possible. also, more than one output can be on at a time for overlapping phases. master clock frequency the clock frequency of the ADP3206 is set with an external resistor connected from the rt pin to ground. the frequency follows the graph in figure 6. to determine the frequency per phase, the clock is to be divided by the number of phases in use. if pwm4 is grounded, then divide the master clock by 3 for the frequency of the remaining phases. if pwm3 and 4 are grounded, then divide by 2. if all phases are in use, divide by 4. output voltage differential sensing the ADP3206 combines differential sensing with a high accuracy vid dac, precision ref output, and a low offset error amplifier to meet intel's imvp-5 specification. during normal mode, the vid dac and error amplifier maintain a worst-case specification of 10 mv over the full operating output voltage and temperature range. for deeper sleep operation, an external resistor divider from the ref pin to fbrtn creates the dprset voltage. this voltage is buffered by a low offset, slew rate limited amplifier that is used to drive the noninverting input of the error amplifier. the core output voltage is sensed between the fb and fbrtn pins. fb should be connected through a resistor to the regulation point, usually the remote sense pin of the microprocessor. fbrtn should be connected directly to the remote sense ground point. the internal vid dac, dprset voltage, and precision ref output are referenced to fbrtn, which has a minimal current of 100 a to allow accurate remote sensing. output current sensing the ADP3206 provides a dedicated current sense amplifier (csa) to monitor the total output current for proper voltage positioning versus load current and for current limit detection. sensing the load current at the output gives the total average current being delivered to the load, which is an inherently more accurate method then peak current detection or sampling the current across a sense element such as the low side mosfet. this amplifier can be configured several ways depending on the objectives of the system: ? output inductor esr sensing without thermistor for lowest cost ? output inductor esr sensing with thermistor to improve accuracy for tracking inductor temperature ? sense resistors for highest accuracy measurements
ADP3206 rev. 0| page 12 of 32 the positive input of the csa is connected to the csref pin, which is connected to the output voltage. the inputs to the amplifier are summed together through resistors from the sensing element (such as the switch node side of the output in- ductors) to the inverting input, cssum. the feedback resistor between cscomp and cssum sets the gain of the amplifier, and a filter capacitor is placed in parallel with this resistor. the gain of the amplifier is programmable by adjusting the feedback resistor to set the lo ad line required by the micro- processor. the current information is then given as the difference of csref ? cscomp. this difference signal is used internally to offset the error amplifier for voltage positioning and as a differential input for the current limit comparator. to provide the best accuracy for current sensing, the csa has been designed to have a low offset input voltage. also, the sensing gain is determined by external resistors so that it can be made extremely accurate. active impedance control mode for controlling the dynamic output voltage droop as a function of output current, a signal proportional to the total output current at the cscomp pin can be scaled to be equal to the droop impedance of the regulator times the output current. this droop voltage is then used to set the input control voltage to the system. the droop voltage is subtracted from the error amplifier offset voltage to tell the error amplifier where the output voltage should be. this differs from previous implementations and allows enhanced feed-forward response current control mode and thermal balance the ADP3206 has individual inputs for each phase which are used for monitoring the current in each phase. this information is combined with an internal ramp to create a current balancing feedback system that has been optimized for initial current balance accuracy and dynamic thermal balancing during operation. this current balance information is independent of the average output current information used for positioning described previously. the magnitude of the internal ramp can be set to optimize the transient response of the system. it is also monitors the supply voltage for feed-forward control for changes in the supply. a resistor connected from the power input voltage to the rampadj pin determines the slope of the internal pwm ramp. detailed information about programming the ramp is given in the applications section. external resistors can be placed in series with individual phases to create an intentional current imbalance if desired, such as when one phase may have better cooling and can support higher currents. resistors r sw1 through r sw4 (see the typical application circuit in figure 1) can be used for adjusting thermal balance. it is best to have the ability to add these resistors during the initial design, so make sure placeholders are provided in the layout. to increase the current in any given phase, make r sw for that phase larger (make r sw = 0 for the hottest phase and do not change during balancing). increasing r sw to only 500 ? makes a substantial increase in phase current. increase each r sw value by small amounts to achieve balance, starting with the coolest phase first. voltage control mode a high gain-bandwidth error amplifier is used for the voltage- mode control loop. during normal mode, the noninverting input voltage is set via the 6-bit vid logic code listed in table 4, while during deeper sleep operation, it is set to track the buffered dprset voltage. the noninverting input voltage is also offset by the droop voltage for offsetting the output voltage as a function of current, commonly known as active voltage positioning. the output of the amplifier is the comp pin, which sets the termination voltage for the internal pwm ramps. the negative input (fb) is tied to the output sense location with a resistor r b and is used for sensing and controlling the output voltage at this point. during normal mode, a current source from the fb pin flowing through r b is used for setting the no- load offset voltage from the vid voltage. the no-load voltage is negative with respect to the vid dac. the main loop compensation is incorporated in the feedback network between fb and comp.
ADP3206 rev. 0| page 13 of 32 table 4. output voltage vs. vid code (x = dont care) vid4 vid3 vid2 vid1 vid0 vid5 v out(nom) 0 1 0 1 0 0 0.8375 v 0 1 0 0 1 1 0.850 v 0 1 0 0 1 0 0.8625 v 0 1 0 0 0 1 0.875 v 0 1 0 0 0 0 0.8875 v 0 0 1 1 1 1 0.900 v 0 0 1 1 1 0 0.9125 v 0 0 1 1 0 1 0.925 v 0 0 1 1 0 0 0.9375 v 0 0 1 0 1 1 0.950 v 0 0 1 0 1 0 0.9625 v 0 0 1 0 0 1 0.975 v 0 0 1 0 0 0 0.9875 v 0 0 0 1 1 1 1.000 v 0 0 0 1 1 0 1.0125 v 0 0 0 1 0 1 1.025 v 0 0 0 1 0 0 1.0375 v 0 0 0 0 1 1 1.050 v 0 0 0 0 1 0 1.0625 v 0 0 0 0 0 1 1.075 v 0 0 0 0 0 0 1.0875 v 1 1 1 1 0 1 1.100 v 1 1 1 1 0 0 1.1125 v 1 1 1 0 1 1 1.125 v 1 1 1 0 1 0 1.1375 v 1 1 1 0 0 1 1.150 v 1 1 1 0 0 0 1.1625 v 1 1 0 1 1 1 1.175 v 1 1 0 1 1 0 1.1875 v 1 1 0 1 0 1 1.200 v 1 1 0 1 0 0 1.2125 v 1 1 0 0 1 1 1.225 v vid4 vid3 vid2 vid1 vid0 vid5 v out(nom) 1 1 0 0 1 0 1.2375 v 1 1 0 0 0 1 1.250 v 1 1 0 0 0 0 1.2625 v 1 0 1 1 1 1 1.275 v 1 0 1 1 1 0 1.2875 v 1 0 1 1 0 1 1.300 v 1 0 1 1 0 0 1.3125 v 1 0 1 0 1 1 1.325 v 1 0 1 0 1 0 1.3375 v 1 0 1 0 0 1 1.350 v 1 0 1 0 0 0 1.3625 v 1 0 0 1 1 1 1.375 v 1 0 0 1 1 0 1.3875 v 1 0 0 1 0 1 1.400 v 1 0 0 1 0 0 1.4125 v 1 0 0 0 1 1 1.425 v 1 0 0 0 1 0 1.4375 v 1 0 0 0 0 1 1.450 v 1 0 0 0 0 0 1.4625 v 0 1 1 1 1 1 1.475 v 0 1 1 1 1 0 1.4875 v 0 1 1 1 0 1 1.500 v 0 1 1 1 0 0 1.5125 v 0 1 1 0 1 1 1.525 v 0 1 1 0 1 0 1.5375 v 0 1 1 0 0 1 1.550 v 0 1 1 0 0 0 1.5625 v 0 1 0 1 1 1 1.575 v 0 1 0 1 1 0 1.5875 v 0 1 0 1 0 1 1.600 v 1 1 1 1 1 x no cpu deep sleep and deeper sleep settings the ADP3206 includes circuitry to perform both deep sleep and deeper sleep functions. during deep sleep, the imvp-5 specification requires that the core output voltage be decreased by a fixed percentage. this decrease is user programmable. the ADP3206 accomplishes this function by forcing the programmed dac voltage on the dpset pin. an external resistor between this pin and ground generates a current that is proportional to the dac voltage. this deep sleep offset current is then mirrored and forced out of the fb pin along with the no- load offset current. this causes the core output voltage to be negative with respect to the vid dac. to enter deep sleep operation, dpslp and dprslp must be low. the ADP3206 also provides a soft transient function to reduce inrush current during transitions into and out of deeper sleep. reducing the inrush current helps decrease the acoustic noise generated by the mlcc input capacitors and inductors due to added stress. the slew rate for the soft transient is set by the external capacitor on the stset pin and the 15 a output current of the low offset buffer. during normal and deep sleep modes, the output of the vid dac is connected to the buffer, thereby forcing the stset voltage to the nominal dac voltage. when the dprslp signal is forced high, the ADP3206 enters into deeper sleep mode. first, the deep sleep offset current is shut off. next, the vid dac output is disconnected from the noninverting input of the error amplifier, while the stset pin is connected. the dprset pin is then connected to the input of the buffer, which causes the stset voltage to slew from the nominal dac voltage to the dprset voltage. because the core voltage follows the noninverting input of the error amplifier, the output voltage transitions to the deeper sleep voltage. to exit deeper sleep, the dprslp pin must be forced low. the dprset pin is then disconnected from the buffer and the vid dac signal is connected. this causes the stset voltage to slew from the dprset voltage to the programmed dac voltage. the core voltage follows this transition. after the stset voltage
ADP3206 rev. 0| page 14 of 32 reaches the programmed dac voltage, the stset pin is dis- connected from noninverting input of the error amplifier, while the vid dac output is connected. during transitions into/out of deeper sleep, the power good circuit is masked to prevent false triggering of the pwrgd signal. the masking time is set by an external capacitor, which is placed between the pgmask pin and ground. this capacitor is discharged to ground during normal operation. during a transition of the dprslp pin, the masking time begins and the capacitor is charged up by a current source. once the voltage on the pgmask pin reaches 3v, the masking time has ended and the pgmask capacitor is reset to ground. if a dprslp transition occurs during a masking event, the capacitor on pgmask is reset to ground to restart the masking time. to minimize power dissipation during deeper sleep, the ADP3206 switches over to single-phase operation. this is accomplished by taking the od2 and pwm2, 3, and 4 outputs low upon the completion of the power good masking time. this allows for all phases to aid in discharging the core output during the soft transient into deeper sleep. when dprslp goes low, the od2 signal immediately goes high, followed by the normal operation of the pwm2 through pwm4 signals. this allows all phases to aid in the charging of the core output back to the deep sleep voltage. soft-start the power-on ramp up time of the output voltage is set with a capacitor and resistor in parallel from the delay pin to ground. the rc time constant also determines the current limit latch-off time as explained in the following section. in uvlo or when sd is a logic low, the delay pin is held at ground. after the uvlo threshold is reached and sd is asserted, the delay cap is charged up with an internal 20 a current source. the output voltage follows the ramping voltage on the delay pin, limiting the inrush current. the soft-start time depends on the value of vid dac and c dly , with a secondary effect from r dly . refer to the applications section for detailed information on setting c dly . when the pwrgd threshold is reached, the soft-start cycle is stopped and the delay pin is pulled up to 3 v. this ensures that the output voltage is at the vid voltage when the pwrgd signals to the system that the output voltage is good. if either sd is taken low or vcc drops below uvlo, the delay cap is reset to ground to be ready for another soft-start cycle. 04651-0-008 figure 8. typical start-up waveforms channel 1: pwrgd, channel 2: v core , channel 3: phase 2 switch node, channel 4: sd current limit, short circuit, and latch-off protection the ADP3206 compares a programmable current limit set point to the voltage from the output of the current sense amplifier. the nominal voltage on the ilimit pin is 1 v. the level of current limit is set with a resistor from the ilimit pin to ground. for four-phase operation during normal mode, the current through the external resistor is internally scaled to give a current limit threshold of 24 mv/a. during deeper sleep mode, the current limit threshold is scaled down to a fraction of the normal mode threshold where the scaling factor is the number of operational phases. fo r example, a four-phase design scales the current limit threshold to 6 mv/a. during any mode of operation, if the difference in voltage between csref and cscomp rises above the current limit threshold, the internal current limit amplifier controls the internal comp voltage to maintain the average output current at the limit. after the limit is reached, the 3 v pull-up on the delay pin is disconnected, and the external delay capacitor is discharged through the external resistor. a comparator monitors the delay voltage and shuts off the controller when the voltage drops below 1.8 v. the current limit latch-off delay time is therefore set by the rc time constant discharging from 3 v to 1.8 v. because the controller continues to cycle the phases during the latch-off delay time, if the current limit is removed before the 1.8 v threshold is reached, the controller returns to normal operation. the recovery characteristic depends on the state of pwrgd. if the output voltage is within the pwrgd window, the controller resumes normal operation. however, if current limit has caused the output voltage to drop below the pwrgd threshold, then a soft-start cycle is initiated.
ADP3206 rev. 0| page 15 of 32 the latch-off function can be reset by both removing and reapplying vcc to the ADP3206, or by pulling the sd pin low for a short time. to disable the current limit latch-off function, the external resistor on the delay pin to ground should be left open. this prevents the delay capacitor from discharging so the 1.8 v threshold is never reached. during start-up when the output voltage is below 200 mv, a secondary current limit is active because the voltage swing of cscomp cannot go below ground. this secondary current limit controls the internal comp voltage to the pwm comparators to 2 v. this limits the voltage drop across the low side mosfets through the current balance circuitry. there is also an inherent per phase current limit that protects individual phases in the case where one or more phases may stop functioning because of a faulty component. this limit is based on the maximum normal-mode comp voltage. 04651-0-009 figure 9. overcurrent latch-off waveforms channel 1: pwrgd, channel 2: v core , channel 3: delay, channel 4: phase 2 switch node dynamic vid the ADP3206 incorporates the ability to dynamically change the vid input while the controller is running. this allows the output voltage to change while the supply is running and supplying current to the load. this is commonly referred to as vid-on-the-fly (otf). a vid-otf can occur under either light load or heavy load conditions. the processor signals the controller by changing the vid inputs in multiple steps from the start code to the finish code. this change can be either positive or negative. when a vid input changes state, the ADP3206 detects the change and ignores the dac inputs for a minimum of 400 ns. this time is to prevent a false code due to logic skew while the6 vid inputs are changing. additionally, the first vid change initiates the pwrgd and crowbar masking functions to prevent a false pwrgd or crowbar event. each vid change resets the voltage on the pgmask capacitor. power good monitoring the power good comparator monitors the output voltage via the csref pin. the pwrgd pin is an open drain output whose high level (i.e., when it is connected to a pull-up resistor) indicates that the output voltage is within the nominal limits based on the vid voltage setting. pwrgd goes low if the output voltage is outside of this specified range. pwrgd is masked during a vid-otf event for a period determined by the pgmask capacitor. output crowbar as part of the protection for the load and output components of the supply, the pwm outputs are driven low (turning on the low-side mosfets) when the output voltage exceeds the upper power good threshold. this crowbar action stops once the output voltage has fallen below the release threshold of approximately 450 mv. turning on the low-side mosfets pulls down the output as the reverse current builds up in the inductors. if the output overvoltage is due to a short of the high side mosfet, this action current limits the input supply or blows its fuse, protecting the microprocessor from destruction. output enable and uvlo the input supply (vcc) to the controller must be higher than the uvlo threshold and the sd pin must be higher than its logic threshold for the ADP3206 to begin switching. if uvlo is less than the threshold or the sd pin is a logic low, the ADP3206 is disabled. this holds the pwm outputs at ground, shorts the delay capacitor to ground, and holds the od1 and od2 pins at ground. proper power supply sequencing must be adhered to during start-up and shutdown of the ADP3206. all input pins must be at ground prior to applying vcc. during the power down sequence, all input pins must be forced to ground prior to vcc ramping down to ground. all output pins should be left in a high impedance state when vcc is off. thermal throttling control the ADP3206 includes a thermal monitoring and masking circuit to detect when a point on the vr has exceeded a user- defined temperature. the thermal monitoring circuit requires an external resistor divider connected between the ref pin and gnd. this divider uses a ntc thermistor and a resistor. the midpoint of the divider is connected to the ttsense pin in order to generate a voltage that is proportional to temperature. an internal circuit compares this voltage to a 1.5 v threshold and outputs a logic level signal at the vrtt output. the vrtt output is designed to drive an external transistor. this transistor should be connected to the processors thermal control circuit.
ADP3206 rev. 0| page 16 of 32 in order to provide temperature hysteresis, a timer is provided to mask the vrtt output. the time is programmed with an external series rc circuit connected between ref and gnd. the midpoint of the rc circuit is connected to the ttmask pin. during shutdown, the ttmask voltage is forced to ground while the vrtt output is forced low. once sd goes high, the voltage on ttsense is compared to an internal threshold of 1.5 v. if the voltage on ttsense rises above the threshold, the vrtt output goes high. during this transition, the masking timer starts. the ttmask voltage now increases based upon the rc time constant. during this charging time, the vrtt signal is latched and remains high regardless of changes in the ttsense voltage. once the ttmask voltage reaches the 1.5 v threshold, the ttmask pin is forced to ground to reset the timer and complete the masking time. in the event that the ttsense voltage goes below the threshold, the above masking time and latching of the new vrtt signal occurs again.
ADP3206 rev. 0| page 17 of 32 21 gnd 22 ttmask 23 ttsense 24 vrtt 25 sw4 26 sw3 27 sw2 28 sw1 29 od2 30 od1 10 dpset 9 dprslp 8 dprset 7 ref 6 stset 5 pgmask 4 comp 3 fb 2 fbrtn 1 vid5 31 pwm4 32 pwm3 33 pwm2 34 pwm1 35 vcc 36 vid4 37 vid3 38 vid2 39 vid1 40 vid0 vr_vid4 vr_vid3 vr_vid2 vr_vid1 vr_vid0 20 cscomp 19 cssum 18 csref 17 ilimit 16 rampadj 15 rt 14 delay 13 sd 12 pwrgd 11 dpslp ADP3206 rsw1* rsw2* rsw3* rsw4* rlim 154k ? 1% rr 280k ? 1% rt 169k ? 1% rdly 390k ? 1% r4 4.7 ? ra 16.2k ? 1% rb 1.58k ? 1% rcs1 35.7k ? 1% rttmask 62k ? cttmask 47nf +v5s rth1 ntc 100k ? 5% r51 6.81k ? 1% vr_vid5 dprslpvr stpcpu +v3.3s core pwrgd vr on prochot cc3 3.3nf ca 470pf c pgmask c stset 2.2nf cb 1200pf rcs2 73.2k 1% rph1 130k 1% rph2 130k 1% rph3 130k 1% rph4 130k 1% in 1 sd 2 drvlsd 3 crowbar 4 vcc 5 bst drvh sw gnd drvl 10 9 8 7 6 adp3419 r13 0 ? c12 4.7 f +v5s c13 0.1 f q13 si7886dp q14 si7886dp q11 si7860dp d11 bar43s q12 si7860dp c14 0.1 f c15 ... c17 3 10 f +vdc l1 0.56 h d12 c11 0.1 f in 1 sd 2 drvlsd 3 crowbar 4 vcc 5 bst drvh sw gnd drvl 10 9 8 7 6 adp3419 r23 0 ? c22 4.7 f +v5s c23 0.1 f q23 si7886dp q24 si7886dp q21 si7860dp d21 bar43s q22 si7860dp c24 0.1 f c25 ... c27 3 10 f +vdc l2 0.56 h d22 c21 1 f in 1 sd 2 drvlsd 3 crowbar 4 vcc 5 bst drvh sw gnd drvl 10 9 8 7 6 adp3419 r33 0 ? c32 4.7 f +v5s c33 0.1 f q33 si7886dp q34 si7886dp q31 si7860dp d11 bar43s q32 si7860dp c34 0.1 f c35 ... c37 3 10 f +vdc l3 0.56 h d32 c31 0.1 f in 1 sd 2 drvlsd 3 crowbar 4 vcc 5 bst drvh sw gnd drvl 10 9 8 7 6 adp3419 r43 0 ? c42 4.7 f c43 0.1 f q43 si7886dp q44 si7886dp q41 si7860dp d41 bar43s q42 si7860dp c44 0.1 f c45 ... c47 3 10 f +vdc l4 0.56 h d42 c41 0.1 f rth ntc 100k ? 5% *for a description of optional r sw resistors, see the theory of operation section. (rth1 is located close to hot spot of the vr circuit) c1 10 f +v5s cfb 47pf rdpset1 43.2k ? 1% rdpset2 16.5k ? 1% r3 3k ? rdpset 97.6k ? 1% c3 1000pf 150pf cdly 56nf +vdc c61 ... c90 30 10 f c6 10nf c51 ... c56 6 330 f 04651-0-010 figure 10. typical imvp-5 application circuit
ADP3206 rev. 0| page 18 of 32 application information the design parameters for a typical intel imvp5-compliant cpu core vr application are as follows: ? maximum input voltage (v inmax ) = 19 v ? minimum input voltage (v inmin ) = 8 v ? output voltage by vid setting (v vid ) = 1.350 v ? nominal output voltage at no load (v onl ) = 1.325 v ? offset voltage (v offset ) = 1.350 v-1.325 v = 0.025 v ? nominal output voltage at 80 a load (v ofl ) = 1.221 v ? duty cycle at maximum input voltage (d min ) = 0.070 ? duty cycle at minimum input voltage (d max ) = 0.166 ? load line slope (r o ) = 1.3 m ? ? static output voltage drop from no load to full load (v ? ) = v onl - v ofl = 1.325 v - 1.221 v = 104 mv ? maximum output current (i o ) = 80 a ? maximum output current step ( ? i o ) = 56 a ? number of phases (n) = 4 ? switching frequency per phase (f sw ) = 280 khz ? deepersleep voltage at no load (v dprslp ) = 0.8v ? deepsleep offset percentage (k os %) = -1.7% setting the clock frequency the ADP3206 uses a fixed-frequency control architecture. the frequency is set by an external timing resistor (r t ). the clock frequency and the number of phases determine the switching frequency per phase, which relates directly to switching losses and the sizes of the inductors and input and output capacitors. in case of a four-phase design, a clock frequency of 1.12 mhz sets the switching frequency to 280 khz per phase. this selection represents trade-off between the switching losses and the minimum sizes of the output filter components. figure 6 shows that to achieve a 1.12 mhz oscillator frequency, r t has to be 169 k ? . alternatively, the value for r t can be calculated using: () ? ? = m 5 . 1 1 pf 83 . 5 1 sw t f n r (1) where 5.83 pf and 1.5 m ? are internal ic component values. for good initial accuracy and frequency stability, it is recommended to use a 1% resistor. soft-start, power good, and current limit latch-off delay times the soft-start and current limit latch-off delay functions share the delay pin, consequently, these two parameters must be considered together. the first step is to set c dly for the soft-start ramp. this ramp is generated with a 20 a internal current source. the value of r dly has a second-order impact on the soft- start time by sinking a portion of the current to ground. however, as long as r dly is kept greater than 200 k ? , this effect is negligible. the value for c dly can be approximated using: vid dly vid dly v t r v c ss ? ? ? ? ? ? ? ? ? = 2 ma 20 (2) where t ss is the desired soft-start time. assuming an r dly of 390 k ? and a desired a soft-start time of 2.2 ms, c dly is 56 nf. once c dly has been chosen, r dly can be recalculated for the current limit latch off time using: dly delay dly c t r = 96 . 1 (3) if the result for r dly is less than 200 k ? , then a smaller soft-start time or longer latch-off time should be considered when c dly is recalculated. in no case should r dly be less than 200 k ? . in this example, a delay time of 10 ms gives r dly = 371 k ? . the closest standard 5% value is 390 k ? . the pwrgd delay, defined as the time period between the v core voltage reaching vid voltage and the assertion of pwrgd signal, is also controlled by the delay pin. the ADP3206 does not assert the pwrgd signal until delay pin voltage reaches about 2.2 v. given the previously calculated values for r delay and c delay , the pwrgd delay is in the range of 2.4 ms to 4 ms. this satisfies the specification range of 1 ms to 10 ms. inductor selection the choice of inductance determines the ripple current in the inductor. less inductance leads to more ripple current, which increases the output ripple voltage and also the conduction losses in the mosfets. however, this allows the use of smaller- size inductors, and for a specified peak-to-peak transient deviation, it allows less total output capacitance. conversely, a higher inductance means lower ripple current and reduced conduction losses, but requires larger-size inductors and more output capacitance for the same peak-to-peak transient deviation. in multiphase converter, the practical value for peak- to-peak inductor ripple current is less than 50% of the maximum dc current in the same inductor. equation 4 shows the relationship between the inductance, oscillator frequency,
ADP3206 rev. 0| page 19 of 32 and peak-to-peak ripple current. equation 5 can be used to determine the minimum inductance based on a given output ripple voltage: l f d v i sw min vid r ? = ) 1 ( (4) ripple sw min min o vid v f d d n r v l ? ? ) 1 ( )) ( 1 ( (5) solving equation 5 for a 10 mv peak-to-peak output ripple voltage yields nh 417 mv 10 khz 280 ) 07 . 0 1 ( )) 07 . 0 4 ( 1 ( m 3 . 1 v 350 . 1 = ? ? ? l if the ripple voltage ends up being less than the initially selected value was, then the inductor can be changed to a smaller value until the ripple value is met. this iteration allows optimal transient response and minimum output decoupling. the smallest possible inductor sh ould be used to minimize the number of output capacitors. choosing a 560 nh inductor is a good choice for a starting point, and it gives a calculated ripple current of 8.0 a. the inductor should not saturate at the peak current of 24 a, and should be able to handle the sum of the power dissipation caused by the average current of 20 a in the winding and also the ac core loss. another important factor in regarding the inductor design is the dcr, which is used for measuring the phase currents. a large dcr causes excessive power losses, while too small of a value leads to increased measurement error. a good rule of thumb is to have the dcr to be about 1 to 1? times of the droop resistance (r o ). for our example, we are using an inductor with a dcr of 1.7 m ? . selecting a standard inductor once the inductance and dcr are known, the next step is to select a standard inductor that comes as close as possible to meeting the overall design goals. it is also important to have the inductance and dcr tolerance specified to keep the accuracy of the system controlled. using 20% tolerance for the inductance and 8% for the dcr (at room temperature) are reasonable assumptions that most manufacturers can meet. power inductor manufacturers the following companies provide surface mount power inductors optimized for high power applications upon request. ? vishay dale electronics, inc. (605) 665-9301 http://www.vishay.com ? panasonic (714) 373-7334 http://www.panasonic.com ? sumida electric company (847) 545-6700 http://www.sumida.com ? nec tokin corporation (510) 324-4110 http://www.nec-tokin.com/ output droop resistance the design requires that the regulator output voltage measured at the cpu pins drops when the output current increases. the specified voltage drop corresponds to a dc output resistance (r o ). the output current is measured by summing the currents of the resistors monitoring the voltage across each inductor and by passing the signal through a low-pass filter. this summer-filter is implemented by the cs amplifier that is configured with resistors r ph(x) (summers), and r cs and c cs (filter). the output resistance of the regulator is set by the following equations, where r l is the dcr of the output inductors: l x ph cs o r r r r = ) ( (6) cs l cs r r l c = (7) one has the flexibility of choosing either r cs or r ph(x) . due to the current drive ability of cscomp pin, the r cs resistance should be larger than 100 k ? . for example, select r cs to be equal to 100 k ? , then solve for r ph(x) by rearranging equation 6. () k 196 k 150 m 3 . 1 m 7 . 1 = = x ph r next, use equation 7 to solve for c cs : nf 2 . 2 k 150 m 7 . 1 nh 560 = = cs c
ADP3206 rev. 0| page 20 of 32 for this example, c cs calculates to 3.3 nf, which is a standard capacitance. in case that the calculated c cs is not a standard value, adjust r cs until standard c cs capacitor value is achieved. for best accuracy, c cs should be a 5% npo capacitor. the standard 1% value for r ph(x) is 130 k ? . inductor dcr temperature correction with the inductor's dcr being used as sense element, and copper wire being the source of the dcr, one needs to compensate for temperature changes of the inductor's winding. fortunately, copper has a well-known temperature coefficient (tc) of 0.39%/c. if r cs is designed to have an opposite sign but equal percentage change in resistance, it cancels the temperature variation of the inductor's dcr. due to the nonlinear nature of ntc thermistors, series resistors, r cs1 and r cs2 (see figure 11) are needed to linearize the ntc and produce the desired temperature coefficient tracking. 18 cscomp ADP3206 cssum c cs r cs1 r cs2 r ph1 r th r ph2 to switch nodes place as close as possible to nearest inductor or low-side mosfet to v out sense r ph3 csref 04651-0-011 17 16 keep this path as short as possible and well away from switch node lines figure 11. temperature compensation circuit values the following procedure and expressions yield values for r cs1 , r cs2 , and r th (the thermistor value at 25c) for a given r cs value. 1. select an ntc to be used based on type and value. because we do not have a value yet, start with a thermistor with a value close to r cs . the ntc should also have an initial tolerance of better than 5%. 2. based on the type of ntc, find its relative resistance value at two temperatures. the temperatures to use that work well are 50c and 90c. we call these resistance values a (a is r th (50c)/r th (25c)) and b (b is r th (90c)/r th (25c)). note that the ntc's relative value is always 1 at 25 c. 3. next, find the relative value of r cs required for each of these temperatures. this is based on the percentage change needed, which we initially make 0.39%/c. we call these r 1 (r 1 is 1/(1+ tc (t 1 - 25))) and r 2 (r 2 is 1/(1 + tc (t 2 - 25))), where tc=0.0039, t1 = 50c and t2 = 90c. 4. compute the relative values for r cs1 , r cs2 , and r th using: ) ( ) 1 ( ) 1 ( ) 1 ( ) 1 ( ) ( b a r a b r b a r a b r b a r r b a r 2 1 1 2 2 1 cs2 ? ? ? ? ? ? + ? ? ? = cs2 1 cs2 cs1 r r a r a r ? ? ? ? = 1 1 ) 1 ( cs1 cs2 th r r r 1 1 1 1 ? ? = (8) 5. calculate r th = r th r cs , then select the closest value of thermistor available. also compute a scaling factor k based on the ratio of the actual thermistor value used relative to the computed one: () () calculated th actual th r r k = (9) 6. finally, calculate values for r cs1 and r cs2 using: cs1 cs cs1 r k r r = )) ( ) 1 (( cs2 cs cs2 r k k r r + ? = (10) for this example, we start with a thermistor value of 100 k ? . looking through available 0603 size thermistors, we can find a vishay nths0603n01n1003jr ntc thermistor with a = 0.3602 and b = 0.09174. from these data we compute r cs1 = 0.3796, r cs2 = 0.7195 and r th = 1.0751. solving for r th yields 107.5 k ? , so we choose 100 k ? , making k = 0.9302. finally, we find r cs1 and r cs2 to be 35.3 k ? and 73.9 k ? . choosing the closest 1% resistor values yields a choice of 35.7 k ? and 73.2 k ? . output offset intel's specification requires that at no load the nominal output voltage of the regulator to be offset to a lower value than the nominal voltage corresponding to the vid code. the offset is set by a constant current source flowing out of the fb pin (i fb ) and flowing through r b . the value of r b can be found using the following equation. the closest standard 1% resistor value is 1.58 k ? . fb offset b i v r = (11) k 67 . 1 a 15 v 025 . 0 = = b r
ADP3206 rev. 0| page 21 of 32 c out selection the required output decoupling for processors and platforms is typically recommended by intel. the following guidelines can also be used if there are both bulk and ceramic capacitors in the system. the first thing is to select the total amount of ceramic capacitance. this is based on the number and type of capacitor to be used. the best location for ceramics is inside the socket; 12 to 18 pieces of size 1206 being the physical limit. others can be placed along the outer edge of the socket as well. combined ceramic values of 200 to 300 f are recommended, and are usually made up of multiple 10 f or 22 f capacitors. select the number of ceramics and find the total ceramic capacitance (c z ). next, there is an upper limit imposed on the total amount of bulk capacitance (c x ) when one considers the vid on-the-fly output voltage stepping (voltage step v v in time t v with error of v err ), and also a lower limit based on meeting the critical capacitance for load release at a given maximum load step ? i o . the imvp-5 specification allows a maximum vcore overshoot (v osmax ) of 50 mv over vid voltage for a step-off load current. z o offset osmax o vid o min x c i v v r v n i l c ? ? ? ? ? ? ? ? ? ? + + ? ) ( (12) () max x c z o v vid v vid v 2 o 2 c l nkr v v t v v r nk l ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + 1 1 2 ? ? ? ? ? ? ? ? = v verr v v n k 1 where to meet the conditions of these expressions and transient response, the esr of the bulk capacitor bank ( r x ) should be less than two times the droop resistance, r o . if the c x(min) is larger than c x(max) , the system does not meet the vid on-the-fly and/or deepersleep exit specification and may require a smaller inductor or more phases (the switching frequency may also have to be increased to keep the output ripple the same). for our example, we use thirty pieces of 10 f 0805 mlc capacitors ( c z = 300 f). the largest vid voltage change is the exit of deepersleep, v core change is 525 mv in 100 s with a setting error of 20 mv. where k = 3.3, solving for the bulk capacitance yields: mf 9 . 1 f 300 a 56 mv 25 mv 50 m 3 . 1 350 . 1 4 a 56 nh 560 ) ( = ? ? ? ? ? ? ? ? ? + + ? min x c using six 330 f panasonic sp capacitors with a typical esr of 7 m ? each yields c x = 1.98 mf with an r x = 1.2 m ? . one last check should be made to ensure that the esl of the bulk capacitors (l x ) is low enough to limit the initial high- frequency transient spike. this is tested using: ph 507 ) m 3 . 1 ( f 300 2 2 = ? x o z x l r c l (14) in this example, l x is about 150 ph for the six sp cap capacitors, which satisfies this limitation. if the l x of the chosen bulk capacitor bank is too large, the number of capacitors must be increased. one should note, for this multimode control technique, an all-ceramic capacitor design can be used as long as the conditions of equations 12, 13 and 14 are satisfied. power mosfets for normal 20 a per phase application, the n-channel power mosfets are selected for two high-side switches and two or three low-side switches per phase. the main selection param- eters for the power mosfets are v gs(th) , q g , c iss , c rss and r ds(on) . because the gate drive voltage (the supply voltage to the adp3419) is 5 v, logic-level threshold mosfets must be used. the maximum output current i o determines the r ds(on) requirement for the low-side (synchronous) mosfets. in the ADP3206, currents are balanced between phases; the current in each low-side mosfet is the output current divided by the total number of mosfets (n sf ). with conduction losses being dominant, the following expression shows the total power being dissipated in each synchronous mosfet in terms of the ripple current per phase (i r ) and average total output current (i o ): () () sf ds sf r sf o sf r n i n n i d p ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ? ? ? = 2 2 12 1 1 (15) knowing the maximum output current and the maximum allowed power dissipation, one can find the required r ds(on) for the mosfet. for so-8 or so-8 compatible packaged mosfets, the junction to ambient (pcb) thermal impedance is 50 c/w. in worst case, the pcb temperature is 70 c to 80 c during heavy load operation of the notebook, a safe limit for p sf is 0.8 w~1.0 w at 120 c junction temperature. thus, for our example (80 a maximum), we find r ds(sf) (per mosfet) < 8.5m ? for two pieces of low-side mosfet. this r ds(sf ) is also at a junction temperature of about 120 c, therefore, the r ds(sf) (per mosfet) should be lower than 6 m ? at room temperature, which gives 8.5 m ? at high temperature. another important factor for the synchronous mosfet is the input capacitance and feedback capacitance. the ratio of the feedback to input needs to be small (less than 10% is recommended) to prevent accidental turn-on of the synchronous mosfets when the switch node goes high.
ADP3206 rev. 0| page 22 of 32 the high-side (main) mosfet has to be able to handle two main power dissipation components; conduction and switching losses. the switching loss is related to the amount of time it takes for the main mosfet to turn on and off, and to the current and voltage that are being switched. basing the switching speed on the rise and fall time of the gate driver impedance and mosfet input capacitance, the following expression provides an approximate value for the switching loss per main mosfet, where n mf is the total number of main mosfets: () iss mf g m f o cc sw mf s c n n r n i v f p = 2 (16) here, r g is the total gate resistance (1.5 ? for the adp3419 and about 0.5 ? for two pieces of typical high speed switching mosfets, making r g = 2 ? ) and c iss is the input capacitance of the main mosfet. the best thing to reduce switching loss is to use lower gate capacitance devices. the conduction loss of the main mosfet is given by the following, where r ds(mf) is the on-resistance of the mosfet: () () mf ds mf r mf mf c r n i n n d p ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ? ? = 2 2 o 12 1 i (17) typically, for main mosfets, one wants the highest speed (low c iss ) device, but these usually have higher on-resistance. one must select a device that meets the total power dissipation (0.8~1.0 w for a single so-8 package) when combining the switching and conduction losses. for our example, we have selected a vishay si7860 device as the main mosfet (eight in total; i.e., n mf = 8), with about c iss = 1560 pf (max) and r ds(mf) = 15 m ? (max at tj = 120 c) and a vishay si7889 device as the synchronous mosfet (eight in total; i.e., n sf = 8), r ds(sf) = 7.9 m ? (max at tj = 120 c). solving for the power dissipation per mosfet at i o = 80 a and i r = 8.0 a yields 700 mw for each synchronous mosfet and 730 mw for each main mosfet. a 3rd synchronous mosfet is an option to further increase the conversion efficiency and reduce thermal stress. one last thing to look at is the power dissipation in the driver for each phase. this is best described in terms of the q g for the mosfets and is given by the following, where q gmf is the total gate charge for each main mosfet and q gsf is the total gate charge for each synchronous mosfet: () sw drv mf gmf sf gsf cc cc f p= n q +n q +i v n 2 ?? ?? ?? (18) also shown is the standby dissipation (i cc times the v cc ) of the driver. for the adp3419, the maximum dissipation should be less than 300 mw, considering its thermal impedance 220 c/w and the maximum temperature increase is 50 c. for our example, with i cc = 2 ma, q gmf = 22.8 nc and q gsf = 84 nc, we find 160 mw dissipation in each driver, which is below the 300 mw dissipation limit. see the adp3419 data sheet for details. ramp resistor selection the ramp resistor (r r ) is used for setting the size of the internal pwm ramp. the value of this resistor is chosen to provide the best combination of thermal balance, stability, and transient response. use this expression to determine a starting value: k 81 3 pf 5 m 2 . 4 5 3 nh 0 60 0.2 3 = = = r r ds d r r r c r a l a r (19) where a r is the internal ramp amplifier gain, a d is the current balancing amplifier gain, r ds is the total low-side mosfet on-resistance, and c r is the internal ramp capacitor value. another consideration in the selection of r r is the size of the internal ramp voltage (see equation 20). for stability and noise immunity, keep this ramp size larger than 0.5 v. taking this into consideration, the value of r r is selected as 280 k ?. the internal ramp voltage magnitude can be calculated using: ( ) () v m 51 . 0 khz 267 pf 5 k 83 3 v 5 1. 125 0. 1 0.2 1 = ? = ? = r sw r r vid r r v f c r v d a v (20) the size of the internal ramp can be made larger or smaller. if it is made larger, stability and transient response improves, but thermal balance degrades. likewise, if the ramp is made smaller, thermal balance improves at the sacrifice of transient response and stability. the factor of three in the denominator of equation 19 sets a minimum ramp size that gives an optimal balance for good stability, transient response, and thermal balance. comp pin ramp there is a ramp signal on the comp pin due to the droop voltage and output voltage ramps. this ramp amplitude adds to the internal ramp to produce the following overall ramp signal at the pwm input. () ? ? ? ? ? ? ? ? ? ? = o x sw r rt r c f n d n v v 1 2 1 (21) for this example, the overall ramp signal is found to be 1.1v.
ADP3206 rev. 0| page 23 of 32 current limit setpoint to select the current limit set point, we need to find the resistor value for r lim . the current limit threshold for the ADP3206 is set with a 1 v source (v lim ) across r lim with a gain of 6 mv/a per phase. r lim can be found using the following: o lim lim lim lim r i n v a r = (22) for values of r lim greater than 500 k ? , the current limit may be lower than expected, so some adjustment of r lim may be needed. here, i lim is the average current limit for the output of the supply. for our example, choosing 120 a for i lim , we find r lim to be 154 k ? , which is a standard 1% resistance. the per phase current limit described earlier has its limit determined by the following: () () 2 r max ds d bias r max comp phlim i r a v v v i ? ? ? ? (23) for the ADP3206, the maximum comp voltage ( v comp(max) ) is 3.3 v, the comp pin bias voltage (v bias ) is 1.2 v, and the current balancing amplifier gain (a d ) is 5. using v r of 1.1 v, and r ds(max) of 4.2 m ? (low-side on-resistance at 150c), we find a per-phase limit of 66 a. this limit can be adjusted by changing the ramp voltage v r . but make sure not to set the per-phase limit lower than the average per-phase current (i lim /n). the per phase initial duty cycle limit at maximum input voltage is: () rt bias max comp min lim v v v d d d ? = = (24) for this example, the duty cycle limit at maximum input voltage is found to be 0.23 when d is 0.07. feedback loop compensation design optimized compensation of the ADP3206 allows the best possible response of the regulator's output to a load change. the basis for determining the optimum compensation is to make the regulator and output decoupling appear as an output impedance that is entirely resistive over the widest possible frequency range, including dc, and equal to the droop resistance (r o ). with the resistive output impedance, the output voltage droops in proportion with the load current at any load current slew rate; this ensures the optimal positioning and allows the minimization of the output decoupling. with the multimode feedback structure of the ADP3206, one needs to set the feedback compen sation to make the converter's output impedance work in parallel with the output decoupling. there are several poles and zeros created by the output inductor and decoupling capacitors (output filter) that need to be compensated for. a type-three compensator on the voltage feedback is adequate for proper compensation of the output filter. the expressions given below are intended to yield an optimal starting point for the design; some adjustments may be necessary to account for pcb and component parasitic effects.(see tuning guide) the first step is to compute the time constants for all of the poles and zeros in the system: ( ) vid o x rt vid rt l ds d o e v r c n v d n l v v r r a r n r ? + + + = 1 2 (25) () x o o x o x a r r r r l r r c t ' ' ? + ? = (26) ( ) x o x b c r r r t ? + = ' (27) e vid sw ds d rt c r v f r a l v t ? ? ? ? ? ? ? ? ? = 2 (28) () o z o x o z x d r c r r c r c c t + ? = ' 2 (29) where, for the ADP3206, r' is the pcb resistance from the bulk capacitors to the ceramics and where r ds is the total low-side mosfet on-resistance per phase. for this example, a d is 5, v rt equals 1.1v, r' is approximately 0.4 m ? (assuming an 8-layer motherboard) and l x is 150 ph for the six panasonic sp capacitors. the compensation values can be solved using the following: b e a o a r r t r n c = (30) a c a c t r = (31) b b b r t c = (32) a d fb r t c = (33) the standard values for these components are subject to the tuning procedure, as introduced in the next section.
ADP3206 rev. 0| page 24 of 32 c in selection and input current di/dt reduction in continuous inductor-current mode, the source current of the high-side mosfet is approximately a square wave with a duty ratio equal to n v out /v in and an amplitude of one-nth of the maximum output current. to prevent large voltage transients, a low esr input capacitor sized for the maximum rms current must be used. the maximum rms capacitor current happens at the lowest input voltage, and is given by a 4 . 9 1 166 . 0 4 1 a 80 66 . 01 1 1 = ? = ? = crms max o max crms i d n i d i (34) in a typical notebook system, the battery rail decouplings are mlcc capacitors or a mixture of mlcc capacitors and bulk capacitors. in this example, the input capacitor bank is formed by 12 pieces of 10 f, 25 v mlcc capacitors with a ripple current rating of about 1a each. 90 efficiency (%) load current (a) 75 80 85 10 20 30 40 50 60 70 80 90 vdc = 8v vdc = 19v 04651-0-012 vdc = 12v figure 12. efficiency of power conversion vs. output current and input voltage deepersleep voltage and transient setting the deepersleep voltage is set on the dprset pin via a resistor divider from v ref voltage, which is 3.0 v. the voltage set on the dprset pin is used as the reference voltage for the error amplifier when dprslp is asserted. considering there is a zero load offset voltage, the voltage on the dprset pin should be v dprset = v offset +v dprslp (35) with v dprslp = 0.8 v and v offset = 25 mv, v dprset = 0.825 v. the suggested current for the dprset pin resistor divider is i dprset =50 a. therefore, the divider resistors are: k 5 . 43 = ? = dprslp dprset ref dprset1 i v v r (36) k 5 . 16 = = dprslp dprset dprset2 i v r (37) the closest 1% resistors are 43.2 k ? and 16.5 k ? . during the transient of entering and exiting deepersleep, the slew-rate of v core reference voltage change is controlled by the stset pin capacitance, which can be calculated as below. dprslp offset vidhfm stset dprslp stset v v v i t c ? ? = 8 . 0 (38) t dprslp is the longest duration of deepersleep exit, specified as 100 s in imvp-5. i stset is the charge and discharge current of the stset pin, and has a value of 15 a. v vidhfm is the highest possible vid voltage the system returns when it exits from deepersleep. it is specified as 1.350 v in imvp-5. therefore, c stset is calculated as 2.4 nf, with the closest standard capacitance 2.2 nf. figure 4 shows the transition from active mode to deepersleep mode. as soon as dprslp is asserted, the v core voltage is gradually discharged to deepersleep voltage (0.8 v). once the transition is completed, the pwm outputs of phase 2, 3, and 4 are disabled, switching the converter to single-phase operation. 04651-0-013 figure 13. transient to deepersleep mode channel 1Cdprslp, channel 2Cvcore (with 1 v offset), channel 3Cswitch node of phase 2, channel 4Csw node of phase 1. figure 5 shows the power conversion efficiency improvement of single-phase operation during deepersleep.
ADP3206 rev. 0| page 25 of 32 efficiency (%) load current (a) 04651-0-014 90 30 50 70 3456 2 1 0 1-phase operation 4-phase operation figure 14. efficiency improvement in deepersleep mode deepsleep offset voltage setting the deepsleep offset voltage is programmed by a resistor on the dpset pin. the voltage on the dpset pin is equal to the vid voltage. when dpslp is asserted, the current programmed on the dpset pin is sourced on the fb pin, resulting in an additional negative offset voltage. the dpset pin resistor should be: fb os offset dpset i v v r % = (39) where v os% is the deepsleep offset percentage, specified as 1.7% in imvp-5. the v offset over i fb term is actually the r b resistance (see output offset section). thus, r dpset is calculated as 98 k ? , with the closest standard resistance 97.6 k ? . pwrgd mask timer setting the pwrgd (power good) mask is programmed by the capacitance on the pgmask pin. during the period of pwrgd masking, there is a source current (i pgmask = 5 a) out of the pgmask pin, to charge a capacitor, c pgmask . pwrgd masking is terminated when the voltage on the pgmask pin reaches v pgmask = 3.0 v. thus, the capacitance on the pgmask pin can be calculated as: pgmask pgmask pgmask pgmask v i t c = (40) in imvp-5, the pwrgd mask time is defined as t pgmask = 100 s resulting in c pgmask = 167 pf. because the specified t pgmask is the maximum length of masking time, please select the next lower standard capacitance: 150 pf. selecting thermal monitor components for single-point hot spot thermal monitoring, simply set r ttset1 equal to the ntc thermistor's resistance at the alarm tempera- ture. for example, if vrtt alarm temperature is 100c and we use a vishay thermistor (nths-0603n011003j), whose resis- tance is 100 k ? at 25 c, and 6.8 k ? at 100 c, then we simply can set r ttset1 = r th1 (100 c) to 6.8 k ? . a dp3206 reference voltage (3.0v) ref t tsense c tt r th1 r ttset1 r r 04651-0-015 figure 15. single-point thermal monitoring multiple-point hot spots thermal monitoring can be implemented as shown in figure 16. if any of the monitored hot spots reaches alarm temperature, vrtt signal is asserted. the following calculation sets the alarm temperature: e temperatur alarm th1 ref fd ref fd ttset1 r v v v v r ? + = 2 1 2 1 (41) where v fd is the forward drop voltage of the parallel diode. because the forward current is very small, the forward drop voltage is very low, i.e., 100 mv. assuming the same 100c alarm temperature used in the single-spot thermal monitoring example, and the same vishay thermistor, then the above formula leads to r ttset = 7.8 k ? , whose closest standard resistor is 7.87 k ? (1%). ADP3206 reference voltage (3.0v) ref c tt r r v rtt t tsense r ttset1 r ttset2 r ttsetn r thn r th2 r th1 v fd 04651-0-016 figure 16. multiple-point thermal monitoring the number of hot spots monitored is not limited as long as the current limit of ref pin (4 ma) is not exceeded. the alarm temperature of each hot spot can be set differently by playing different rttset1, rttset2, rttset n .
ADP3206 rev. 0| page 26 of 32 according to imvp-5, the shortest duration of assertion and de-assertion of vrtt single is 1 ms (t vrtt = 1 ms). this vrtt duration is programmed by the rc timer (r ttmask , c ttmask ) on the ttmask pin. if the rc timer is charged by the vcc voltage (5.0 v), then the rc timer can be set according to the following formula: r ttmask c ttmask = 2.8 t vrtt (42) select a standard capacitance c ttmask = 47 nf, and then the above formula leads to r ttmask = 59.6 k ? , whose next larger standard resistor is 62 k ? (5%). tuning procedure for ADP3206 1. build circuit based on compensation values computed from design spreadsheet. 2. hook-up dc load to circuit, turn on and verify operation. check for jitter at no-load and full-load. dc loadline setting 3. measure output voltage at no-load (v nl ). verify it is within tolerance. 4. measure output voltage at full-load and at cold (v flcold ). let board set for ~10 minutes at full-load and measure output (v flhot ). if there is a change of more than a few millivolts, adjust r cs1 and r cs2 using equations 43 and 44. () () ) ( ) ( flhot nl flcold nl old cs2 new cs2 v v v v r r ? ? = (43) 5. repeat step 4 until cold and hot voltage measurements remain the same. 6. measure output voltage from no-load to full-load using 5 a steps. compute the load line slope for each change and then average to get overall load line slope (r omeas ). 7. if r omeas is off from r o by more than 0.05 m ? , use the following to adjust the r ph values; () () o omeas old ph new ph r r r r = (45) 8. repeat steps 6-7 to check load line and repeat adjustments if necessary. 9. once complete with dc load line adjustment, do not change r ph , r cs1 , r cs2 , or r th for rest of procedure. 10. measure output ripple at no-load and full-load with scope and make sure it is within spec. ac loadline setting 11. remove dc load from circuit and hook up dynamic load. 12. hook up scope to output voltage and set to dc coupling with time scale at 100 s/div. 13. set dynamic load for a transient step of about 40 a at 1 khz with 50% duty cycle. 14. measure output waveform (may have to use dc offset on scope to see waveform). try to use vertical scale of 100 mv/div or finer. 15. you see a waveform that looks something like figure 17. use the horizontal cursors to measure v acdrp and v dcdrp as shown. do not measure the undershoot or overshoot that happens immediately after the step. v acdrp v dcdrp 04835-0-012 figure 17. ac loadline waveform 16. if the v acdrp and v dcdrp are different by more than a couple of millivolts, use the following to adjust c cs . you may need to parallel different values to get the right one because there are limited standard capacitor values available (it is a good idea to have locations for two capacitors in the layout for this). () () dcdrp acdrp old cs new cs v v c c = (46) 17. repeat steps 15-16 and repeat adjustments if necessary. once complete, do not change c cs for the rest of the procedure. 18. set dynamic load step to maximum step size (do not use a step size larger than you need) and verify output waveform is square (which means v acdrp and v dcdrp are equal). note: makes sure load step slew rate and turn-on are set for a slew rate of ~150-250 a/s (for example, a load step of 50 a should take 200-300 ns) with no overshoot. some dynamic loads have an excessive turn-on overshoot if a minimum current is not set properly (this is an issue if you are using a vtt tool).
ADP3206 rev. 0| page 27 of 32 initial transient setting 19. with dynamic load still set at maximum step size, expand scope time scale to see 2-5 s/div. you see a waveform that may have two overshoots and one minor undershoot (see figure 18). here, v droop is the final desired value. v droop v tran1 v tran2 04835-0-013 figure 18. transient setting waveform, load step 20. if both overshoots are larger than desired, try making the following adjustments in this order (noteif these adjustments do not change the response, you are limited by the output decoupling). check the output response each time you make a change as well as the switching nodes (to make sure it is still stable). a. make ramp resistor larger by 25% (r ramp ). b. for v tran1 , increase c b or increase switching frequency. c. for v tran2 , increase r a and decrease c a both by 25%. 21. for load release (see figure 19), if v tranrel is larger than the imvp-5 specification, you do not have enough output capacitance. you either need more capacitance or to make the inductor values smaller (if you change inductors, you need to start the design over using the spreadsheet and this tuning guide). v droop v tranrel 04835-0-014 figure 19. transient setting waveform, load release figure 20 shows the typical transient response using these compensation values. 04651-0-020 (a) 04651-0-021 (b) figure 20. typical transient response for design example (a) load step, (b) load release
ADP3206 rev. 0| page 28 of 32 layout and component placement the following guidelines are recommended for optimal performance of a switching regulator in a pc system. general recommendations for good results, at least a four-layer pcb is recommended. this should allow the needed versatility for control circuitry interconnections with optimal placement, power planes for ground, input, and output power, and wide interconnection traces in the rest of the power delivery current paths. keep in mind that each square unit of 1 ounce copper trace has a resistance of ~0.53 m ? at room temperature. whenever high currents must be routed between pcb layers, vias should be used liberally to create several parallel current paths so that the resistance and inductance introduced by these current paths is minimized and the via current rating is not exceeded. if critical signal lines (including the output voltage sense lines of the ADP3206) must cross through power circuitry, it is best if a signal ground plane can be interposed between those signal lines and the traces of the power circuitry. this serves as a shield to minimize noise injection into the signals at the expense of making signal ground a bit noisier. an analog ground plane should be used around and under the ADP3206 for referencing the components associated with the controller. this plane should be tied to the nearest output de- coupling capacitor ground and should not be tied to any other power circuitry to prevent power currents from flowing in it. the components around the ADP3206 should be located close to the controller with short traces. the most important traces to keep short and away from other traces are the fb and cssum pins. see figure 2 for details on layout for the cssum node. the output capacitors should be connected as closely as possible to the load (or connector) that receives the power (e.g., a microprocessor core). if the load is distributed, the capacitors should also be distributed, and generally in proportion to where the load tends to be more dynamic. avoid crossing any signal lines over the switching power path loop, described below. power circuitry the switching power path should be routed on the pcb to encompass the shortest possible length in order to minimize radiated switching noise energy (i.e., emi) and conduction losses in the board. failure to take proper precautions often results in emi problems for the entire pc system as well as noise-related operational problems in the power converter control circuitry. the switching power path is the loop formed by the current path through the input capacitors and the power mosfets including all interconnecting pcb traces and planes. the use of short and wide interconnection traces is especially critical in this path for two reasons: it minimizes the inductance in the switching loop, which can cause high-energy ringing, and it accommodates the high current demand with minimal voltage loss. whenever a power dissipating component (for example, a power mosfet) is soldered to a pcb, the liberal use of vias, both directly on the mounting pad and immediately surrounding it, is recommended. two important reasons for this are: improved current rating through the vias, and improved thermal performance from vias extended to the opposite side of the pcb where a plane can more readily transfer the heat to the air. make a mirror image of any pad being used to heat sink the mosfets on the opposite side of the pcb to achieve the best thermal dissipation to the air around the board. to further improve thermal performance, the largest possible pad area should be used. the output power path should also be routed to encompass a short distance. the output power path is formed by the current path through the inductor, the output capacitors, and the load. for best emi containment, a solid power ground plane should be used as one of the inner layers extending fully under all the power components. signal circuitry the output voltage is sensed and regulated between the fb pin and the fbrtn pin (which connects to the signal ground at the load). in order to avoid differential mode noise pickup in the sensed signal, the loop area shou ld be small. thus the fb and fbrtn traces should be routed adjacent to each other atop the power ground plane back to the controller. the feedback traces from the switch nodes should be connected as close as possible to the inductor. the csref signal should be kelvin connected to the center point of the copper bar which is the v core common node for the inductors of all the phases. the ADP3206 has a metal pad in th e back side of the package. this metal pad is not a ground node. do not ground this metal pad. in addition, vias under the ADP3206 are not recommended, because the metal pad may short between vias.
ADP3206 rev. 0| page 29 of 32 outline dimensions 1 40 10 11 31 30 21 20 bottom view 4.25 4.10 sq 3.95 top view 6.00 bsc sq pin 1 indicato r 5.75 bsc sq 12 max 0.30 0.23 0.18 0.20 ref seating plane 1.00 0.85 0.80 0.05 max 0.02 nom coplanarity 0.08 0.80 max 0.65 typ 4.50 ref 0.50 0.40 0.30 0.50 bsc pin 1 indicator 0.60 max 0.60 max 0.25 min compliant to jedec standards mo-220-vjjd-2 figure 21. 40-lead frame chip scale package [lfcsp] (cp-40) dimensions shown in millimeters
ADP3206 rev. 0| page 30 of 32 ordering guide model temperature package package description package option ADP3206jcpz-reel 1 0c to +100c lead frame chip scale package cp-40 1 z = pb-free part.
ADP3206 rev. 0| page 31 of 32 notes
ADP3206 rev. 0| page 32 of 32 notes ? 2004 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d04651-0-4/04(0)

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